The present invention relates to a radar system, and particularly to a video signal processor for extracting video data from a radar signal which is input from an antenna and is pre-processed.
Radar systems transmit an electromagnetic wave in a specific form, such as a pulse-modulated sine wave, and detect the properties of a reflected signal FIG. 1 is a block diagram for describing a general radar system.
Referring to FIG. 1, an antenna 101 is time-division-operated to emit radio waves in a specific form and to receive the reflected waves. A pulse modulator 104 generates the radio waves in a specific form, that is, as a pulse-modulated sine wave. The radio wave generated from pulse modulator 104 is applied to antenna 101 via a transmitter 103 and a duplexer 102 and is emitted into the atmosphere via antenna 101. Here, duplexer 102 functions to switch the modes of antenna 101. Antenna 101 is used as a transmitting antenna for a predetermined period and then as a receiving antenna for another predetermined period. That is, antenna 101 is set to a transmitting mode for the first predetermined period and is then set to a receiving mode for the other predetermined period by duplexer 102. Meanwhile, the received reflected wave is applied to a mixer 106 via a low-noise RF amplifier 105. Mixer 106 mixes a local oscillating signal generated from a local oscillator 107 and the output signal of low-noise RF amplifier 105, so as to convert the output signal of low-noise RF amplifier 105 to an intermediate frequency (IF) signal. An IF amplifier 108 amplifies the output signal of mixer 106, with the gain of the amplifier being controlled according to a signal applied from an automatic gain controller (AGC) incorporated in a pre-processor 109. In a radar system, pre-processor 109 and a video signal processor 111 basically function to detect target data in the reflected (received) signal. Here, pre-processor 109 and video signal processor 111 perform various algorithms for maintaining a constant false alarm rate (CFAR).
Pre-processor 109 has a sensitivity time control portion (STC), a fast time constant portion (FTC), and an automatic gain control portion (AGC). The STC and FTC remove various types of clutter which are present in a received radar signal and the AGC controls the gain of IF amplifier 108. Here, pre-processor 109 applies a first radar signal 116 processed by all of STC, FTC and AGC and second radar signal 115 processed by only STC, FTC excluding AGC, to video signal processor 111.
FIG. 2A is a detailed block diagram of a conventional video signal processor 111 for a radar system. The processor comprises an A/D converting portion 201, a cell-averaging circuit portion 202 and a buffer memory portion 203.
In FIG. 2A, A/D converting portion 201 converts the first and second radar signals 115 and 116 of analog into the first and second radar signals of digital using A/D converters 204 and 205, respectively. Here, the A/D converters are operated by a sampling clock of a specific frequency which is closely related to the range resolution. Therefore, in order to improve range resolution, A/D converters capable of performing higher-frequency sampling operations, are required. However, as the A/D converter's sampling clock frequency is tied to device characteristics, there is generally a maximum sampling clock frequency at which the A/D converter can operate stably. Therefore, in a conventional radar system, range resolution is limited by the maximum frequency of the sampling clock at which an adopted A/D converter can be operated.
Cell averaging circuit portion 202 removes unknown background noise and background clutter from data output from A/D converters 204 and 205, and outputs the data to buffer memories 208 and 209. The cell averaging circuit portion adaptively sets a threshold value for determining whether a signal is target data or not. Here, the method for adaptively setting the threshold value is called cell averaging.
Buffer memories 208 and 209 store the output of cell averaging circuit portion 202 and output the stored data on demand of a scan converter or tracking processor. Here, the scan converter converts polar-coordinate video data stored in buffer memory 208 into rectangular-coordinate video data, and applies the converted data to a raster-scan-type display. The tracking processor calculates the speed and acceleration of a target using video data stored in buffer memory 209, so as to estimate the bearing of the target.
FIG. 2B is a detailed block diagram of the cell averaging circuit portion shown in FIG. 2A. The cell averaging circuit portion has a first delay line 210, a second delay line 213, an output cell 212, a first adder 211, a second adder 214, a first constant multiplier 215, a second constant multiplier 217, a maximum value detector 216 and a threshold value processor 218.
In FIG. 2B, first and second delay lines 210 and 213 are composed of series-connected delay devices. In the delay devices, from the reference of output cell 212, data corresponding to a previous range and data corresponding to a succeeding range are sequentially stored. The stored data is added in first and second adders 211 and 214, respectively. The output of first adder 211 is multiplied by a specific constant .alpha.1 in first constant multiplier 215, and the output of second adder 214 is multiplied by a specific constant .alpha.2 in second constant multiplier 217. Here, the constants .alpha.1 and .alpha.2 are varied according to the number of cells added by first and second adders 211 and 214 and the maximum data level regarded as a false target signal. Maximum value detector 216 detects the higher value between the outputs of first and second constant multipliers 215 and 217 and applies the detected value to threshold value processor 218 as a threshold value. Only when the data of output cell 212 is above the threshold value, threshold value processor 218 outputs the data as video data. When the data is not above the threshold value, the threshold value processor outputs non-signal data representing that no target exists.
As described above, in the conventional video signal processor, since the range resolution is limited according to the sampling clock frequency permitted by an A/D converter. Also, as cell averaging is performed via fixed form of hardware, multiplied constants and the number of added ranges cannot be adaptively adjusted according to the time-variant situation. The cell averaging circuit shown in FIG. 2B performs only one cell averaging algorithm, while a radar system is generally required to change the cell averaging algorithm itself according to the circumstances of the region to be detected.